The antenna effect is the name given to the phenomena of induced voltages that can collect on partially processed leads. The effect is partially prevalent during plasma processing e.g., etching, deposition and ashing and ion implantation, and can lead to damage to thin gate oxide regions of the device under construction.
Process-induced charging and ensuing gate oxide damage constitutes a significant yield and reliability detriment for submicron CMOS technology. Problems occur at many stages of processing, but are aggravated by long lead lengths at poly lead definition following polysilicon deposition. As devices are further scaled to reduced geometries, the gate oxide becomes progressively thinner and hence more susceptible to damage, even at reduced voltages. The etch step is particularly problematic for metal, especially during lead separation and differentiation, and for plasma enhanced interlevel dielectric depositions.
Charge accumulation on partially processed leads, and the resultant voltage increase, can cause voltage overstress and result in charge trapping in gate oxides and gate oxide breakdown. Previously, simple n+/p or p+/n junction diodes were used to protect oxides from the antenna effect during VLSI processing. As gate oxides have become thinner in reduced geometry devices, such as 0.5 micron and further reduced geometry devices, gate oxide damage tends to occur prior to protective junction diode breakdown. As a consequence, use of the diode for protection from the antenna effect discussed above becomes ineffective as the gate oxide thickness is scaled below thicknesses of about 100 .ANG. (Angstroms), which have breakdown voltages on the order of about 16 volts or less. Accordingly, it would be desirable to provide an alternative type of protective device that is operable to protect gate oxides having thicknesses below about 100 .ANG., as can be expected to be required in future generation ULSI (i.e., less than 100 .ANG. gate oxide thickness) and further reduced geometry devices.
FIG. 1 depicts a portion 10 of a conventional semiconductor device which gives rise to the charge induced antenna effect. It is to be appreciated that the illustrated device can be constructed in accordance with a variety of known processing techniques, the specific manner of processing not being relevant to the following discussion. The semiconductor portion 10 includes a substrate 12 that is typically formed from a semiconductive material such as silicon which is doped with a p-type impurity. The semiconductor substrate 12 can also be formed from a variety of other semiconductive materials, such as GaAs and HgCdTe, for which the principles of the present invention that are set forth below are likewise applicable. In the illustrated structure, a VLSI device under construction is designated generally by reference character 16, and the associated protective component is designated generally by reference character 20. The protective component that is presently utilized in the art is typically an n.sup.+ /p or a p.sup.+ /n junction diode.
The device portion 10 includes field oxide regions 24a-24c, which can be developed in the substrate 12 in a conventional manner, such as by thermal growth, to a thickness of about 400-1,000 nm. Interposed between the field oxide regions 24a and 24b is a gate oxide region 26 that is typically thermally grown to a thickness of about 4-20 nm. A layer of polysilicon 28 is patterned and applied in an appropriate manner over the gate oxide 26 and doped with an appropriate impurity, such as phosphorus, to render the polysilicon 28 layer conductive. Dielectric film 30 is applied over the polysilicon and underlying field oxide regions 24 and is patterned and etched to create a channel 22 such as a via or contact opening that extends from an upper surface of the dielectric 30 to an upper surface of the polysilicon 28 and a channel 33 that extends from an upper surface of the dielectric 30 to moat region 36. The vias 22 and 33 can be filled with an appropriate metal conductor 34, such as an alloy of aluninum or copper, to establish electrical contact between non-adjacent levels of the device 10.
The illustrated junction diode 20 includes moat region 36 which is typically doped with an n.sup.+ impurity to produce an n.sup.+ /p junction diode. The junction diode 20 is electrically connected to the device gate oxide 26 by metal lead line 34, thereby permitting the junction diode to preferentially leak electric current from the gate oxide region 26 and thereby protect the gate oxide 26 from currents that may pass through the device. Such a protection scheme is suitable for device geometries in excess of about 0.8.mu. (microns). However, for reduced geometries, particularly device geometries below about 0.8.mu. (microns), for which the corresponding gate oxide layers are of reduced thickness and therefore more susceptible to charge-induced leakage currents, such protection schemes have not proven satisfactory to adequately protect the structural integrity of the gate oxide.